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CVE-2020-0574
Published: Mar 12, 2020
Modified: Aug 4, 2024
PUBLISHED
Description
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
| Vendor | Product | Versions |
|---|---|---|
Intel | Intel(R) MAX(R) 10 FPGA | affected All versionsaffected See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html |
References
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