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CVE-2024-24853
Published: Aug 14, 2024
Modified: Aug 16, 2024
PUBLISHED
CVSS v3.1
7.2
HIGH
Description
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
| Vendor | Product | Versions |
|---|---|---|
n/a | Intel(R) Processor | affected See references |
Weaknesses (CWE)
CVSS v3.1 Details
CVSS v3.1 Vector
CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
Attack Vector
Local
Attack Complexity
High
Privileges Required
High
User Interaction
Required
Scope
Changed
Confidentiality
High
Integrity
High
Availability
High
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