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CVE-2025-0647
Published: Jan 14, 2026
Modified: Jan 20, 2026
PUBLISHED
Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
| Vendor | Product | Versions |
|---|---|---|
Arm | Neoverse-N2 | affected 0 |
Arm | Neoverse-V3AE | affected 0 |
Arm | Neoverse-V3 | affected 0 |
Arm | Neoverse-V2 | affected 0 |
Arm | Cortex-X925 | affected 0 |
Arm | Cortex-X4 | affected 0 |
Arm | Cortex-X3 | affected 0 |
Arm | Cortex-X2 | affected 0 |
Arm | Cortex-A710 | affected 0 |
Arm | C1-Premium | affected 0 |
Arm | C1-Ultra | affected 0 |
Weaknesses (CWE)
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