CWE-1261
Improper Handling of Single Event Upsets
Description
The hardware logic does not effectively handle when single-event upsets (SEUs) occur.
{"xhtml:p":["Technology trends such as CMOS-transistor down-sizing, use of \n new materials, and system-on-chip architectures continue to increase the \n sensitivity of systems to soft errors. These errors are random, and \n their causes might be internal (e.g., interconnect coupling) or external \n (e.g., cosmic radiation). These soft errors are not permanent in nature \n and cause temporary bit flips known as single-event upsets (SEUs). \n SEUs are induced errors in circuits caused when charged particles lose \n energy by ionizing the medium through which they pass, leaving behind a \n wake of electron-hole pairs that cause temporary failures. If these \n failures occur in security-sensitive modules in a chip, it might \n compromise the security guarantees of the chip. For instance, these \n temporary failures could be bit flips that change the privilege of\n\t a regular user to root."]}
Parent Weaknesses (ChildOf)
Related Weaknesses
Common Consequences
Scope
Impact
DoS: Crash, Exit, or Restart, DoS: Instability, Gain Privileges or Assume Identity, Bypass Protection Mechanism
Potential Mitigations
Implement triple-modular redundancy around security-sensitive modules.
SEUs mostly affect SRAMs. For SRAMs storing security-critical data, implement Error-Correcting-Codes (ECC) and Address Interleaving.
Applicable Platforms
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