CWE-1332
Improper Handling of Faults that Lead to Instruction Skips
Description
The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.
{"xhtml:p":["The operating conditions of hardware may change\n in ways that cause unexpected behavior to occur,\n including the skipping of security-critical CPU\n instructions. Generally, this can occur due to\n electrical disturbances or when the device operates\n outside of its expected conditions.","In practice, application code may contain\n\t\t\t conditional branches that are security-sensitive (e.g.,\n\t\t\t accepting or rejecting a user-provided password). These\n\t\t\t conditional branches are typically implemented by a\n\t\t\t single conditional branch instruction in the program\n\t\t\t binary which, if skipped, may lead to effectively\n\t\t\t flipping the branch condition - i.e., causing the wrong\n\t\t\t security-sensitive branch to be taken. This affects\n\t\t\t processes such as firmware authentication, password\n\t\t\t verification, and other security-sensitive decision\n\t\t\t points.","Attackers can use fault injection techniques to\n\t\t\t alter the operating conditions of hardware so that\n\t\t\t security-critical instructions are skipped more\n\t\t\t frequently or more reliably than they would in a\n\t\t\t \"natural\" setting."]}
Parent Weaknesses (ChildOf)
Related Weaknesses
Common Consequences
Scope
Impact
Bypass Protection Mechanism, Alter Execution Logic, Unexpected State
Potential Mitigations
Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.
Design strategies for ensuring safe behavior if instructions attempt to be skipped.
Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.
Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.
Use redundant operations or canaries to detect and respond to faults.
Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.
CVE-2019-15894fault injection attack bypasses the verification mode, potentially allowing arbitrary code execution.
Applicable Platforms
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