CWE Database
/

CWE-1420

Back to CWE list

CWE-1420

Exposure of Sensitive Information during Transient Execution

Base
Incomplete

Description

A processor event or prediction may allow incorrect operations (or correct operations with incorrect data) to execute transiently, potentially exposing data over a covert channel.

{"xhtml:p":["When operations execute but do not commit to the processor's\n\t\t\t\t\tarchitectural state, this is commonly referred to as transient\n\t\t\t\t\texecution. This behavior can occur when the processor mis-predicts an\n\t\t\t\t\toutcome (such as a branch target), or when a processor event (such as\n\t\t\t\t\tan exception or microcode assist, etc.) is handled after younger\n\t\t\t\t\toperations have already executed. Operations that execute transiently\n\t\t\t\t\tmay exhibit observable discrepancies (CWE-203) in covert channels\n\t\t\t\t\t[REF-1400] such as data caches. Observable discrepancies of this kind\n\t\t\t\t\tcan be detected and analyzed using timing or power analysis\n\t\t\t\t\ttechniques, which may allow an attacker to infer information about the\n\t\t\t\t\toperations that executed transiently. For example, the attacker may be\n\t\t\t\t\table to infer confidential data that was accessed or used by those\n\t\t\t\t\toperations.","Transient execution weaknesses may be exploited using one of two\n\t\t\t\t\tmethods. In the first method, the attacker generates a code sequence\n\t\t\t\t\tthat exposes data through a covert channel when it is executed\n\t\t\t\t\ttransiently (the attacker must also be able to trigger transient\n\t\t\t\t\texecution). Some transient execution weaknesses can only expose data\n\t\t\t\t\tthat is accessible within the attacker's processor context. For\n\t\t\t\t\texample, an attacker executing code in a software sandbox may be able\n\t\t\t\t\tto use a transient execution weakness to expose data within the same\n\t\t\t\t\taddress space, but outside of the attacker's sandbox. Other transient\n\t\t\t\t\texecution weaknesses can expose data that is architecturally\n\t\t\t\t\tinaccessible, that is, data protected by hardware-enforced boundaries\n\t\t\t\t\tsuch as page tables or privilege rings. These weaknesses are the\n\t\t\t\t\tsubject of CWE-1421.","In the second exploitation method, the attacker first identifies a\n\t\t\t\t\tcode sequence in a victim program that, when executed transiently, can\n\t\t\t\t\texpose data that is architecturally accessible within the victim's\n\t\t\t\t\tprocessor context. For instance, the attacker may search the victim\n\t\t\t\t\tprogram for code sequences that resemble a bounds-check bypass\n\t\t\t\t\tsequence (see Demonstrative Example 1). If the attacker can trigger a\n\t\t\t\t\tmis-prediction of the conditional branch and influence the index of\n\t\t\t\t\tthe out-of-bounds array access, then the attacker may be able to infer\n\t\t\t\t\tthe value of out-of-bounds data by monitoring observable discrepancies\n\t\t\t\t\tin a covert channel."]}

Common Consequences

Scope

Confidentiality

Impact

Read Memory

Potential Mitigations

Architecture and Design

The hardware designer can attempt to prevent transient execution from causing observable discrepancies in specific covert channels.

Requirements

Processor designers may expose instructions or other architectural features that allow software to mitigate the effects of transient execution, but without disabling predictors. These features may also help to limit opportunities for data exposure.

Requirements

Processor designers may expose registers (for example, control registers or model-specific registers) that allow privileged and/or user software to disable specific predictors or other hardware features that can cause confidential data to be exposed during transient execution.

Requirements

Processor designers, system software vendors, or other agents may choose to restrict the ability of unprivileged software to access to high-resolution timers that are commonly used to monitor covert channels.

Build and Compilation

Isolate sandboxes or managed runtimes in separate address spaces (separate processes). For examples, see [REF-1421].

Build and Compilation

Include serialization instructions (for example, LFENCE) that prevent processor events or mis-predictions prior to the serialization instruction from causing transient execution after the serialization instruction. For some weaknesses, a serialization instruction can also prevent a processor event or a mis-prediction from occurring after the serialization instruction (for example, CVE-2018-3639 can allow a processor to predict that a load will not depend on an older store; a serialization instruction between the store and the load may allow the store to update memory and prevent the prediction from happening at all).

Build and Compilation

Use control-flow integrity (CFI) techniques to constrain the behavior of instructions that redirect the instruction pointer, such as indirect branch instructions.

Build and Compilation

If the weakness is exposed by a single instruction (or a small set of instructions), then the compiler (or JIT, etc.) can be configured to prevent the affected instruction(s) from being generated, and instead generate an alternate sequence of instructions that is not affected by the weakness. One prominent example of this mitigation is retpoline ([REF-1414]).

Build and Compilation

Use software techniques that can mitigate the consequences of transient execution. For example, address masking can be used in some circumstances to prevent out-of-bounds transient reads.

Build and Compilation

Use software techniques (including the use of serialization instructions) that are intended to reduce the number of instructions that can be executed transiently after a processor event or misprediction.

Documentation

If a hardware feature can allow incorrect operations (or correct operations with incorrect data) to execute transiently, the hardware designer may opt to disclose this behavior in architecture documentation. This documentation can inform users about potential consequences and effective mitigations.

CVE-2017-5753

Microarchitectural conditional branch predictors may allow operations to execute transiently after a misprediction, potentially exposing data over a covert channel.

CVE-2021-0089

A machine clear triggered by self-modifying code may allow incorrect operations to execute transiently, potentially exposing data over a covert channel.

CVE-2022-0002

Microarchitectural indirect branch predictors may allow incorrect operations to execute transiently after a misprediction, potentially exposing data over a covert channel.

Applicable Platforms

Not Language-Specific

Security Training

Train your team to recognize and prevent security threats with our comprehensive security awareness program.

Start Training

Vulnerability Scanning

Discover vulnerabilities in your applications and infrastructure before attackers do.

Scan Now