CWE-1299

The lack of protections on alternate paths to access control-protected assets (such as unprotected shadow registers and other external facing unguarded interfaces) allows an attacker to bypass existing protections to the asset that are only performed against the primary path.

{"xhtml:p":["An asset inside a chip might have access-control\n protections through one interface. However, if all paths to\n the asset are not protected, an attacker might compromise\n the asset through alternate paths. These alternate paths\n could be through shadow or mirror registers inside the IP\n core, or could be paths from other external-facing\n interfaces to the IP core or SoC.","Consider an SoC with various interfaces such as UART,\n SMBUS, PCIe, USB, etc. If access control is implemented for\n SoC internal registers only over the PCIe interface, then\n an attacker could still modify the SoC internal registers\n through alternate paths by coming through interfaces such\n as UART, SMBUS, USB, etc. ","Alternatively, attackers might be able to bypass\n existing protections by exploiting unprotected, shadow\n registers. Shadow registers and mirror registers typically\n refer to registers that can be accessed from multiple\n addresses. Writing to or reading from the aliased/mirrored\n address has the same effect as writing to the address of\n the main register. They are typically implemented within an\n IP core or SoC to temporarily hold certain data. These data\n will later be updated to the main register, and both\n registers will be in synch. If the shadow registers are not\n access-protected, attackers could simply initiate\n transactions to the shadow registers and compromise system\n security. "]}

Applicable Platforms